`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:42:06 02/19/2014 
// Design Name: 
// Module Name:    user_logic_i_tb 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 10ns / 1ns
module user_logic_i_tb;
    localparam                              C_SLV_DWIDTH = 32;
    localparam                              C_NUM_REG = 4;

	// Inputs
    reg                                      bus_clk;
	reg                                      bus_reset;
	reg      [0 : C_SLV_DWIDTH -1]           bus_data;
	reg      [0 : C_SLV_DWIDTH/8-1]          bus_be;
    reg      [0 : C_NUM_REG-1]               bus_rdce;
    reg      [0 : C_NUM_REG-1]               bus_wrce;

    // Outputs
    wire     [0 : C_SLV_DWIDTH -1]           ip_data;
    wire                                     ip_rd_ack;
    wire                                     ip_wr_ack;
    wire                                     ip_error;

	// Bidirs
    wire                                     SDA; 
    wire                                     SCL;
    

     // slave net list
     reg                           slv_rst;     
     reg                           slv_clk;
     reg                           slv_start;
     reg                           slv_stop;
     reg                           slv_read;
     reg                           slv_write;
     reg                           slv_send_ack;
     reg     [7 : 0]               slv_send_data;
     reg     [6 : 0]               slv_addr;
     reg                           slv_reg_exist;
     
     wire                          slv_free;
     wire                          slv_ready;
     wire    [7 : 0]               slv_data_out;
    


    user_logic #(C_SLV_DWIDTH, C_NUM_REG) USER_LOGIC_I_TB(
        .SDA(SDA),
        .SCL(SCL),
        .Bus2IP_Clk(bus_clk),
        .Bus2IP_Reset(bus_reset),
        .Bus2IP_Data(bus_data),
        .Bus2IP_BE(bus_be),
        .Bus2IP_RdCE(bus_rdce),
        .Bus2IP_WrCE(bus_wrce),
        .IP2Bus_Data(ip_data),
        .IP2Bus_RdAck(ip_rd_ack),
        .IP2Bus_WrAck(ip_wr_ack),
        .IP2Bus_Error(ip_error)
    );
    
    
    i2c_core_v02 I2C_SLAVE_TEST_BENCH(
       .sys_clk(slv_clk),
       .sys_rst(slv_rst),
       .start(slv_start),
       .stop(slv_stop),
       .read(slv_read),
       .write(slv_write),
       .send_ack(slv_send_ack),
       .mstr_din(slv_send_data),
       .slv_a0(slv_addr[0]),
       .slv_a1(slv_addr[1]),
       .slv_a2(slv_addr[2]),
       .slv_a3(slv_addr[3]),
       .slv_a4(slv_addr[4]),
       .slv_a5(slv_addr[5]),
       .slv_a6(slv_addr[6]),
       .reg_exist(svl_reg_exist),
       
       .sda(SDA),
       .scl(SCL),
       
       .free(slv_free),
       .ready(slv_ready),
       .slv_dout(slv_data_out)
    );
    
    // initial statement for i2c slave for read operation
    initial begin
       slv_read <= 0;
       slv_start <= 0;
       slv_stop <= 1;
       slv_rst <= 1;

       #355;
       slv_rst <= 0;
       slv_addr <= 7'h5;
       slv_read <= 1;
       slv_write <= 0;
       slv_send_ack <= 1;
       slv_send_data <= 0;
       slv_reg_exist <= 1;
       slv_start <= 1;
       slv_stop <= 0;
    end
    
    always #4 slv_clk = (!slv_clk) && slv_read;
    
    
    // initial statement for i2c master for write operation
	initial begin
		// Initialize Inputs
		bus_clk <= 0;
		bus_reset <= 1;

		// 
		#100 bus_reset <= 0;		
       
        #150;
        bus_data <= 32'b10101010_01010101_10100000_00000000; //Chip address + Register address, check byte order
        bus_wrce <= 4'b1000;
        bus_be <= 4'b1111;
        
        #250;
        bus_data <= 32'h0a; //data byte
        bus_wrce <= 4'b0100;
        bus_be <= 4'b0001;

        #350
        bus_data <= 32'h00000002; //command register
        bus_wrce <= 4'b0010;
        bus_be <= 4'b1111;
        
        #1000
        bus_rdce <= 4'b0001; //read status register
	end
	
	always #4 bus_clk = !bus_clk;
      
endmodule
